Field
Embodiments of the invention generally relate to an apparatus and method for removing particles from substrates or wafers, more particularly, to a cleaning article and a method of using the same for chemical mechanical polishing.
Description of the Related Art
The geometry of semiconductor devices has decreased dramatically in size since such devices were first introduced several decades ago. Integrated circuits have generally followed the two year/half-size rule (often called “Moore's Law”) which states that the number of devices fitting on a chip will double every two years. Today's wafer fabrication plants are routinely producing integrated circuits having 0.5 and even 0.35 micron feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
During deposition and processing of material layers making up these semiconductor devices, improved control over criteria such as particle generation and contamination is necessary to ensure that deposited layers meet the stringent specifications of manufacturers. In order to meet processing demands created by such small scale geometry devices, new technology for substrate processing equipment is constantly being developed. For example, as device sizes become smaller and integration density increases, issues not previously considered important are emerging as areas of concern. One such issue is backside wafer contamination.
Particle contamination on the backside of wafers has become a serious issue in advanced microelectronics manufacturing for several reasons. One reason is that particles on the backside of the wafer can cause cross contamination and electrical contact failures in interconnect structures.
A second reason for the importance to minimize wafer backside particle contamination is change in wafer planarity associated with such contamination. Specifically, particles present on the backside of the wafer can impact control over the critical dimension (CD) in lithographic processes by causing wafer warpage. The depth of focus in sub-half micron lithography is approximately ±0.5 μm, and factors such as field image curvature, circuit topography, wafer flatness and auto-focus errors reduce the usable focus margin. Therefore, ensuring the planarity of wafers during the lithographic process becomes more critical in obtaining tight CD control.
Anti-reflective coatings (ARC) formed by plasma-enhanced chemical vapor deposition (PECVD) have been widely used to control CD during photolithography processing steps by suppressing over 99% of light reflected from a substrate. In general however, wafers that have received an ARC film must generally be subjected to additional processing steps in order to remove particles on the wafer backside before the wafer is exposed to lithography steps.
Therefore, there is a need in the art for methods and apparatuses which reduce particle contamination on the wafer backside prior to lithography processes.